1. Field of the Invention
The present invention relates to a level shifting circuit for converting a logical level.
2. Description of Related Art
FIG. 10 is a circuit diagram to show a conventional level shifting circuit. In a semiconductor device using two types of voltage sources, a low voltage source (VCCL) and a high voltage source (VCCH), the level shifting circuit serves as a circuit which converts the logical level of the voltage VCCL into the logical level of the voltage VCCH (VCCL less than VCCH). In FIG. 10, reference sign IN_L denotes an input signal having the logical level of the voltage VCCL, sign OUT_H denotes an output signal having the logical level of the voltage VCCH, signs INV1001_L and INV1002_L denote inverters operating by the low voltage source (VCCL), sign INV1003 denotes an inverter operating by the high voltage source (VCCH), signs MP1001 and MP1002 denote high-voltage P-type transistors and signs MN1001 and MN1002 denote high-voltage N-type transistors.
FIG. 11 is a waveform chart to show an operation of the conventional level shifting circuit.
Next, an operation will be discussed.
The operation of the level shifting circuit shown in FIG. 10 will be discussed below, referring to the waveform chart of FIG. 11. In the following discussion, the logic High level of the voltage VCCL is represented as xe2x80x9cH_lxe2x80x9d level, the logic High level of the voltage VCCH is represented as xe2x80x9cH_hxe2x80x9d level and the logic Low level (0 V) of these voltages are represented as xe2x80x9cLxe2x80x9d.
In a state where the input signal IN_L is stationary at the xe2x80x9cLxe2x80x9d level, a node N1001 has the xe2x80x9cH_lxe2x80x9d level and a node N1002 has the xe2x80x9cLxe2x80x9d level, and the high-voltage N-type transistor MN1001 is in an ON state and the high-voltage N-type transistor MN1002 is in an OFF state. Further, a node N1003 has the xe2x80x9cLxe2x80x9d level and a node N1004 has the xe2x80x9cH_hxe2x80x9d level, and the high-voltage P-type transistor MP1001 is in the OFF state and the high-voltage P-type transistor MP1002 is in the ON state. The output signal OUT_H has the xe2x80x9cLxe2x80x9d level.
When the input signal IN_L changes from the xe2x80x9cLxe2x80x9d level to the xe2x80x9cH_lxe2x80x9d level (t0 of FIG. 11), the node N1001 comes into the xe2x80x9cLxe2x80x9d level and the node N1002 comes into the xe2x80x9cH_lxe2x80x9d level by the operations of the inverters INV1001_L and INV1002_L (1, 2 of FIG. 11) and the high-voltage N-type transistor MN1001 comes into the OFF state and the high-voltage N-type transistor MN1002 comes into the ON state. At this time, since the high-voltage P-type transistor MP1002 remains in the ON state, the potential of the node N1004 falls to a voltage value V0 obtained by dividing the voltage VCCH by the ON-resistance of the high-voltage P-type transistor MP1002 and the ON-resistance of the high-voltage N-type transistor MN1002 (3 of FIG. 11). When the potential of the node N1064 becomes VCCHxe2x88x92VthP (VthP represents a threshold voltage of the high-voltage P-type transistor) or lower, the high-voltage P-type transistor MP1001 comes into the ON state and the node N1003 is charged up to the voltage VCCH (4 of FIG. 11) and when the potential of the node N1004 becomes the threshold voltage of the inverter INV1003 or lower, the out put signal OUT_H becomes xe2x80x9cH_hxe2x80x9d level (5 of FIG. 11). Further; since the node N1003 is charged up to the voltage VCCH, the high-voltage P-type transistor MP1002 comes into the OFF state and the node N1004 is completely discharged to 0 V (6 of FIG. 11).
When the input signal IN_L changes from the xe2x80x9cH_lxe2x80x9d level to the xe2x80x9cLxe2x80x9d level (t1 of FIG. 11), a series of operation is performed, almost like the above, where the node N1001 changes to the xe2x80x9cH_lxe2x80x9d level and the node N1002 changes to the xe2x80x9cLxe2x80x9d level (11, 12 of FIG. 11), the high-voltage N-type transistor MN1001 comes into the ON state and the high-voltage N-type transistor MN1002 comes into the OFF state, the potential of the node N1003 falls to V0 (13 of. FIG. 11), the high-voltage P-type transistor MP1002 comes into the ON state, the potential of the node N1004 rises up to the voltage VCCH (14 of FIG. 11), and then when the potential of the node N1004 becomes the threshold voltage of the inverter INV1003 or higher, the output signal OUT_H changes to the xe2x80x9cLxe2x80x9d level: (15 of FIG. 11) and the potential of the node N1003 changes to 0 V (16 of FIG. 11).
As discussed above, there is a case in the conventional level shifting circuit, where the high-voltage P-type transistor MP1001 and the high-voltage N-type transistor MN1001 come into the ON state at the same time or where the high-voltage P-type transistor MP1002 and the high-voltage N-type transistor MN1002 come into the ON state at the same time (3, 13 of FIG. 11), and the voltage V0 of the node N1001 or the node N1002 at that time should be VCCHxe2x88x92VthP or lower. Assuming that the ON-resistance of the high-voltage P-type transistor is RonP and the ON-resistance of the high-voltage N-type transistor is RonN, since V0=VCCH*RonN/(RonP+RonN), it is necessary to satisfy a relation RonP greater than RonN in order to set V0 to a low value to some degree. Further, assuming that the channel width of a transistor is W and the channel length thereof is L, since the ON-resistance thereof is in proportion to L/W, it is necessary to set the channel width W smaller and/or the channel length L larger in order to increase the ON-resistance and it is necessary to set the channel width W larger and/or the channel length L smaller in order to decrease the ON-resistance.
With refinement of semiconductor integrated circuits, a power supply voltage used in a semiconductor chip decreases and a difference between this power supply voltage and a power supply voltage for external output signals of the semiconductor chip is widened. The above discussed level shifting circuit is also used for, e.g., converting a logical signal of the low voltage source (VCCL) into a logical signal of the high voltage source (VCCH) for external output inside the semiconductor chip. Since a low-voltage transistor used in a circuit operating by the low voltage source (VCCL) is designed to perform an optimum operation with a low voltage and has a low breakdown voltage, there is a possibility that the low-voltage transistor may be broken when a high voltage is applied thereto. For this reason, a high-voltage transistor having a high breakdown voltage is used for a level shifting circuit connected to a high voltage source (VCCH). A threshold voltage of the high-voltage transistor is higher than that of a low-voltage transistor. When the voltage VCCL of the low voltage source becomes lower, the difference between the voltage VCCL and the threshold voltage (VthN) of the high-voltage N-type transistors MN1001 and MN1002 becomes smaller, and this leads to a problem that the high-voltage N-type transistor MN1001 or the MN1002 does not come into the ON state even if the node N1001 or the node N1002 becomes xe2x80x9cH_lxe2x80x9d level respectively.
Further, even when the voltage VCCL is equal to the threshold voltage (VthN) of the high-voltage N-type transistors MN1001 and MN1002 or higher, since a gate source voltage (VCCL) at the time when;the high-voltage N-type transistors MN1001 and MN1002 are in the ON state is lower than a gate-source voltage (xe2x88x92VCCH) at the time when the high-voltage P-type transistors MP1001 and MP1002 are in the ON state, the ON-resistance RonN of the high-voltage N-type transistor is hard to reduce even if L/W of the high-voltage N-type transistors MN1001 and MN1002 is made smaller, and this tendency is accelerated as the difference between the voltage VCCH and the voltage VCCL becomes larger. Therefore, in order to satisfy the relation RonP greater than RonN, it is necessary to set the ON-resistance RonP extremely high. Since the nodes N1001 and N1002 are charged by the high-voltage P-type transistors MP1001 and MP1002 (4, 14 of FIG. 11), however, the charging speed becomes lower when the ON-resistance RonP is extremely high, and this causes a problem that a delay time of the output signal OUT_H from the input signal IN_L may increase.
In contrast to this, it is possible to satisfy the relation RonP greater than RonN with RonP kept low to some degree by setting L/W of the high-voltage N-type transistors MN1001 and MN1002 extremely smaller than L/W of the high-voltage P-type transistors MP1001 and MP1002. Since a value (RonP+RonN) becomes small in this case, however, a through current which flows when the high-voltage P-type transistor MP1001 and the high-voltage N-type transistor MN1001 come into the ON state at the same time or the high-voltage P-type transistor MP1002 and the high-voltage N-type transistor MN1002 come into the ON state at the same time becomes large and this increases the power consumption.
The present invention is intended to solve the above described problem and it is an object of the present invention to provide a level shifting circuit which realized an increase of the potential difference allowing the logic-level conversion: and a reduction of the delay time and the through current.
In the level shifting circuit in accordance with the present invention, the discharging means is made up of a first high-voltage N-type transistor and a second high-voltage N-type transistor whose gates are biased respectively in a predetermined voltage and whose drains are connected to a first and second nodes respectively; and a first low-voltage N-type transistor and a second low-voltage N-type transistor whose drains are connected to sources of the first and second high-voltage N-type transistors respectively, whose gates are connected to the complementary input signal and whose sources are grounded respectively, and the predetermined voltage is set to an intermediate voltage between a threshold voltage of the first and second high-voltage N-type transistors and a breakdown voltage of the first and second low-voltage N-type transistors.
Therefore; according to the present invention, since gate voltages of the first and second high-voltage N-type transistors are always higher than the threshold voltage thereof and discharges of the first and second nodes are controlled by the first and second low-voltage N-type transistors, it is possible to avoid the problem that the first or second node is not discharged, even if a first voltage source becomes as low as the threshold voltage.
Further, since a voltage equal to or higher than the breakdown voltage of the first and second low-voltage N-type transistors is not applied to the drains of the first and second low-voltage N-type transistors, it is possible to avoid breakage of the first and second low-voltage N-type transistors even if a difference between a second voltage source and the first voltage source becomes larger.
Thus, the present invention produces an effect of providing a level shifting circuit which allows an increase in convertible potential difference.